The present invention relates generally to a semiconductor memory device and more particularly to circuitry for selecting a word line in a memory cell array.
In semiconductor devices, increased integration and improved processing techniques have improved operating speeds. As operating speeds of a central processing unit (CPU) increases, it becomes desirable to reduce the time required for reading and writing data to a memory cell of a semiconductor memory device.
A boosted potential can be applied to a word line in order to write, read, or refresh data in a memory cell. This can improve operational speeds by increasing the data signal stored in a memory cell by increasing the amount of charge that can be stored on a storage capacitor. The boosted potential may also increase speeds by decreasing the resistance of a memory cell transistor.
When reading or writing is finished, the potential on the word line is lowered (typically to a ground potential). In order to improve speeds, it is desirable to discharge the word line as quickly as possible, so that a precharge operation can be more quickly executed. This can decrease the memory cell access cycle time.
Referring now to FIG. 1, a block schematic diagram of a conventional DRAM is shown and given the general reference character 10.
Conventional DRAM 10 includes four memory banks (B1 to B4), main word decoders (XDEC1 to XDEC4), RA drivers (RAD1 to RAD5), and sub-word drivers (SWD1 to SWD20).
Main word decoders (XDEC1 to XDEC4) receive row addresses (X2 to Xj) and provide main word lines MWL. For example, main word decoder XDEC1 provides main word lines (MWL00 to MWL0i). Main word decoder XDEC2 provides main word lines (MWL10 to MWL1i). Main word decoder XDEC3 provides main word lines (MWL20 to MWL2i). Main word decoder XDEC4 provides main word lines (MWL30 to MWL3i).
A main word line MWL from one of main word decoders (XDEC1 to XDEC4) is selected based on the value of row addresses (X2 to Xj). When selected, a main word line MWL transitions to a high level.
RA drivers (RAD1 to RAD5) receive row addresses (X0 and X1) and control signal RAE and generate sub-word select signals (RA00 to RA42). Sub-word select signals are received by sub-word drivers (SWD1 to SWD20). Sub-word drivers (SWD1 to SWD20) then select a sub-word line (not shown in FIG. 1) in each bank (B1 to B4) based on the selected main word line MWL and sub-word select signals (RA00 to RA42) selected.
Each memory bank (B1 to B4) includes four cell arrays (CELL0 to CELL15) and five sense amplifier rows (SA0 to SA19). Bank B1 includes cell arrays (CELL0 to CELL3) and sense amplifier rows (SA0 to SA4). Bank B2 includes cell arrays (CELL4 to CELL7) and sense amplifier rows (SA5 to SA9). Bank B3 includes cell arrays (CELL8 to CELL11) and sense amplifier rows (SA10 to SA14). Bank B4 includes cell arrays (CELL12 to CELL15) and sense amplifier rows (SA15 to SA19).
When receiving a high sub-word select signal (RA00 to RA42) and a high main word line MWL, a sub-word driver (SWD1 to SWD20) selects a sub-word line (not shown) in an adjacent cell array, such that a cell array in each bank has an active sub-word line during an activation cycle.
Sub-word drivers (SWD5 to SWD16) select a sub-word line in two adjacent cell arrays. For example, sub-word driver SWD5 selects a sub-word line in both cell array (CELL0 and CELL4) when one of main word lines (MWL00 to MWL0i) is high (activated) and one of RA signals (RA11 and RA13) is high (activated).
Sub-word drivers (SWD1 to SWD20) include end sub-word drivers (SWD1 to SWD4 and SWD17 to SWD20) that select a sub-word line in the adjacent end cell array. For example, sub-word driver SWD1 selects a sub-word line in cell array CELL0 when one of main word lines (MWL00 to MWL0i) is high (activated) and one of RA signals (RA00 and RA02) is high (activated).
When row addresses (X1 and X0) have the value {low, low} respectively, RA signals (RA00, RA20, and RA40) become high, while other RA signals remain low. Assuming, main word decoder XDEC1 has received a row address (X2 to Xj) that activates one of main word lines (MWL00 to MWL0i), a sub-word line in cell array CELL0 is activated by sub-word decoder SWD1, a sub-word line in cell arrays (CELL4 and CELL8) is activated by sub-word decoder SWD9, and a sub-word line in cell array CELL12 is activated by sub-word decoder SWD17.
When row addresses (X1 and X0) have the value {low, high} respectively, RA signals (RA11 and RA31) become high, while other RA signals remain low. Assuming, main word decoder XDEC1 has received a row address (X2 to Xj) that activates one of main word lines (MWL00 to MWL0i), a sub-word line in cell arrays (CELL0 and CELL4) is activated by sub-word decoder SWD5, and a sub-word line in cell arrays (CELL8 and CELL12) is activated by sub-word decoder SWD13.
When row addresses (X1 and X0) have the value {high, low} respectively, RA signals (RA02, RA22, and RA42) become high, while other RA signals remain low. Assuming, main word decoder XDEC1 has received a row address (X2 to Xj) that activates one of main word lines (MWL00 to MWL0i), a sub-word line in cell array CELL0 is activated by sub-word decoder SWD1, a sub-word line in cell arrays (CELL4 and CELL8) is activated by sub-word decoder SWD9, and a sub-word line in cell array CELL12 is activated by sub-word decoder SWD17.
When row addresses (X1 and X0) have the value {high, high} respectively, RA signals (RA13 and RA33) become high, while other RA signals remain low. Assuming, main word decoder XDEC1 has received a row address (X2 to Xj) that activates one of main word lines (MWL00 to MWL0i), a sub-word line in cell arrays (CELL0 and CELL4) is activated by sub-word decoder SWD5, and a sub-word line in cell arrays (CELL8 and CELL12) is activated by sub-word decoder SWD13.
In this way, one cell array (CELL0 to CELL15) is selected in each bank (B1 to B4). Sense amplifier rows (SA0 to SA19) adjacent to selected banks detect data values stored in memory cells connected to the selected sub-word lines. For example, if cell arrays (CELL0, CELL4, CELL8, and CELL12) are selected, respective adjacent sense amplifier rows will sense the data values in the selected memory cells. Sense amplifier rows (SA0 and SA1) sense data from cell array CELL0. Sense amplifier rows (SA5 and SA6) sense data from cell array CELL4. Sense amplifier rows (SA10 and SA11) sense data from cell array CELL8. Sense amplifier rows (SA15 and SA16) sense data from cell array CELL12.
Although in FIG. 1, RA drivers (RAD1 to RAD5) are shown to output RA signals (RA00 to RA42), complementary RA signals (RAB00 to RAB42) are also generated, but not shown to avoid unduly cluttering the figure.
Referring now to FIG. 2, a block schematic diagram of a portion of conventional DRAM 10 is set forth.
The portion of conventional DRAM 10 includes a portion of cell array CELL0, sub-word decoders (SWD1 and SWD5), and sense amplifier rows (SA0 and SA1).
Each sub-word decoder (SWD1 and SWD5) includes a plurality of sub-decoder blocks SB. For example, sub-word decoder SWD1 includes sub-decoder blocks (SB0000 to SB0i02). RA-drivers (RAD1 and RAD2) generate RA signals (RA00 to RA03) that select predetermined sub-decoder blocks SB.
Cell array CELL0 includes a plurality of memory cells arranged in rows and columns. Each memory cell is connected to receive a sub-word line SWL. Each memory cell is connected to a bit line BT. Two examples of memory cells are illustrated as memory cells (M1 and M2) which are connected to sub-word line SWL0000. Memory cells (M1 and M2) include a memory cell transistor and a memory cell capacitor. The memory cell transistor is an n-type insulated gate field effect transistor (IGFET). Each memory cell capacitor has one terminal connected to a predetermined potential, such as ground or xc2xd Vcc, as just two examples, and another terminal connected to a source of the memory cell transistor. Each memory cell transistor has a gate connected to a sub-word line SWL and a drain connected to a bit line BT.
The quantity of charge stored on the memory cell capacitor determines the logic level of the data stored. Data is written to or read from a memory cell by turning on the memory cell transistor and electrically connecting a bit line BT to a memory cell capacitor to transfer charge to or from the memory cell capacitor.
Bit line pairs are connected to a sense amplifier. For example, bit lines (BT1 and BT2) form one bit line pair connected to sense amplifier SA1.
Each main word line (MWL00 to MWL0i) is connected to two sub-decoder blocks SB in each row of sub-word decoder (SWD1, SWD5, . . . ). Each sub-decoder blcok SB is connected to drive a sub-word line SWL in each adjacent cell array CELL. For example, sub-decoder SB0000 is connected to drive sub-word line SWL0000 within cell array CELL0. However, sub-decoder block SB0001 is connected to drive sub-word line SWL0001 within cell array CELL0 and also connected to drive a sub-word line in cell array CELL4.
Sub-decoder blocks (SB0000 to SB0003) are all connected to receive main word line MWL00. RA-drivers (RAD1 and RAD2) collectively select only one of sub-decoder blocks (SB0000 to SB0003). Thus, when main word line MWL00 is activated, one of sub-word lines (SWL0000 to SWL0003) will be selected based which one of RA signals (RA00 to RA03) is activated. In this way, each main word line MWL is selectively connected to drive one of four sub-word lines SWL in each cell array CELL. Thus, there are four times more sub-word lines SWL within a cell array CELL than there are main word lines MWL connected to sub-word drivers SWD adjacent to a cell array CELL.
It is understood that only a few main word lines MWL, sub-word lines SWL, memory cells (M1 and M2), bit lines BT, sub-decoder blocks SB, and sense amplifiers SA are illustrated in FIG. 2 to avoid unduly cluttering the figure.
Other cell arrays CELL and sub-word decoders SWD illustrated in FIG. 1, are constructed in generally the same manner as illustrated in FIG. 2.
A y-selector circuit (not illustrated) can be used to select a sense amplifier SA to provide a data path between a cell array CELL and an external data pin (not shown). A y-selector receives a column address and selects a sense amplifier SA based on the column address value.
Referring now to FIG. 3, a circuit schematic diagram of a sub-decoder block is set forth and given the general reference character SB.
Sub-decoder block SB includes transistors (T1 to T4). Transistors (T1 to T4) are n-type IGFETs. Sub-decoder block SB can be used as sub-decoder block SB0000 in FIG. 2.
Transistor T1 has a source connected to receive main word line MWL00, a drain connected to a gate of transistor T2 at node A, and a gate connected to power supply potential. Transistor T2 has a drain connected to RA signal RA00 and a source connected to sub-word line SWL0000 at node B. Transistor T3 has a source connected to receive main word line MWL00, a drain connected to sub-word line SWL0000 and a gate connected to receive RA signal RA00. Transistor T4 has a drain connected to sub-word line SWL0000, a source connected to ground, and a gate connected to receive complementary RA signal RAB00.
When at a logic high, the potential levels of RA signal RA00 and complementary RA signal RAB00, main word line MWL00 are boosted supply potentials. Likewise, the power supply potential connected to the gate of transistor T1 is a boosted power supply potential.
Sub-decoder blocks SB within sub-word decoders (SWD1 to SWD5) illustrated in FIG. 2 have generally the same structure as sub-decoder block SB illustrated in FIG. 3.
Referring now to FIG. 4, a timing diagram illustrating the operation of sub-decoder block SB is set forth.
The timing diagram of FIG. 4 illustrates the operation of sub-decoder block SB0000 when memory cell M1 of FIG. 2 is accessed. The timing diagram includes row address XADD, main word line MWL00, control signal RAE, RA signal RA00, complementary RA signal RAB00, voltage at node A, and sub-word line SWL0000.
Initially main word line MWL00, control signal RAE, and RA signal RA00 are low. Complementary RA signal RAB00 is high. With complementary RA signal RAB00 high, transistor T4 is turned on and sub-word line SWL0000 is maintained at a low potential.
At time t100, row address XADD may transition to a value that causes row decoder XDEC1 to activate main word line MWL00. At time t101, row decoder XDEC1 activates main word line MWL00 and main word line MWL00 transitions to a high level.
Because transistor T1 is turned on the voltage at node A follows the voltage on main word line MWL00.
At time t103, control signal RAE transitions high. This allows RA-driver RAD1 to drive RA signal RA00 to a high level and complementary RA signal RAB00 to a low level. The states of RA signal RA00 and complementary RA signal RAB00 are determined by values of row addresses (X0 and X1).
Transistor T1 operates to allow transistor T2 to be self-booting. Transistor T1 allows the gate of transistor T2 to receive a high potential prior to RA signal RA00 transitioning high. Thus, at time t103, when RA signal RA00 transitions high, the gate capacitance of transistor T2 couples the rising potential of RA signal RA00 to node A. Thus, node A potential rises along with the RA signal RA00. As the potential at node A rises to within a threshold voltage of the gate potential of transistor T1, transistor T1 turns off and node A remains booted to a high potential. This allows transistor T2 to pass the full potential of RA signal RA00 to sub-word line SWL0000.
Because complementary RA signal RAB00 is low at this time, transistor T4 is turned off. On other sub-decoder blocks SB within sub-word decoders (SWD1 to SWD4) that receive RA signal RA00 and complementary RA signal RAB00, it is necessary to provide a conductive path from unselected sub-word lines SWL to ground. Transistor T3 serves this function. When RA signal RAB00 transitions high, transistor T3 provides a path to ground when the corresponding main word line MWL is low. This prevents unselected sub-word lines SWL from floating.
After data is read or written to the addressed memory cell M1, control signal RAE returns low. Control signal RAE or row address enable has a predetermined pulse width based on the time required to read or write data from a selected memory cell. This is illustrated at time t104 in FIG. 4.
RA-driver RAD1 receives the low control signal RAE, which causes RA signal RA00 to return low and complementary RA signal RAB00 to return high. With RAB00 high, transistor T4 is turned on and sub-word line SWL0000 is discharged to ground. At the same time, the potential at node A falls along with the potential of RA signal RA00. This is illustrated at time t104 in FIG. 4. It is noted that transistor T2 is on when RA signal RA00 transitions low. Thus, sub-word line is also discharged through transistor T2 by way of RA signal RA00.
Subsequently, at time t106, row address XADD can change and main word line MWL00 transitions low. Because transistor T1 is on, the potential at node A follows main word line MWL00 to a low level, such as ground.
The current paths for discharging a sub-word line SWL when transitioning from selected to unselected will now be explained.
Referring now to FIG. 5, a circuit schematic diagram of a sub-decoder block SB is set forth. Sub-decoder block SB illustrates three current paths through which charge can be removed from sub-word line SWL0000.
Current path 1 illustrates current flowing from sub-word line SWL0000 through transistor T4 to ground. Current path 2 illustrates current flowing from sub-word line SWL0000 through transistor T2 to RA signal RA00. Current path 3 illustrates current flowing from sub-word line SWL0000 through transistor T3 to main word line MWL00.
Referring now to FIG. 6, a timing diagram of illustrating signals for sub-decoder block SB when the sub-word line SWL is in a non-selected state is set forth.
The timing diagram of FIG. 6 includes main word line MWL00, RA signal RA00, complementary RA signal RAB00, potential at node A, and sub-word line SWL0000.
In the non-selected state, main word line MWL00 and RA signal RA00 are both low. Complementary RA signal RAB00 is high.
With main word line MWL00 low, the potential at node A is also low. With the potential at node A low, transistor T2 is turned off. With RA signal RA00 low, transistor T3 is turned off. Thus, current paths (2 and 3) of FIG. 5 are disabled.
However, with complementary RA signal RAB00 high, transistor T4 is turned on, and a conduction path to ground is formed through transistor T4. Thus, the current path 1 of FIG. 5 is enabled. Any charge removed from sub-word line SWL0000 goes through current path 1.
In this case, transistor T4 may only be used to keep sub-word line SWL0000 at a ground level. Thus, under these conditions, transistor T4 does not need to sink a large amount of current and can therefore be a relatively small device.
Referring now to FIG. 7, a timing diagram of illustrating signals for sub-decoder block SB when the sub-word line is in a non-selected state is set forth.
The timing diagram of FIG. 7 includes main word line MWL00, RA signal RA00, complementary RA signal RAB00, potential at node A, and sub-word line SWL0000.
In the non-selected state, RA signal RA00 is low. Complementary RA signal RAB00 is high. However, main word line MWL00 transitions from low to high at time t200 and returns low at time t201. With transistor T1 turned on, the potential at node A generally follows main word line MWL00.
Before time t200, any charge removed from sub-word line SWL0000 goes through current path 1 as illustrated in FIG. 5. However, between the times t200 and t201, transistor T2 turns on. Thus, from time t200 to time t2001, charge removed from sub-word line SWL0000 goes through current paths (1 and 2) as illustrated in FIG. 5.
Referring now to FIG. 8, a timing diagram of illustrating signals for sub-decoder block SB when the sub-word line is in a non-selected state is set forth.
The timing diagram of FIG. 8 includes main word line MWL00, RA signal RA00, complementary RA signal RAB00, potential at node A, and sub-word line SWL0000.
In the non-selected state main word line MWL00 is low. Because main word line MWL00 is low, the potential at node A remains low and transistor T2 remains turned off. However, RA signal RA00 transitions from low to high at time t202 and returns low at time t203. Likewise, complementary RA signal RAB00 transitions from high to low at time t202 and returns high at time t203.
Before time t202, any charge removed from sub-word line SWL0000 goes through current path 1 as illustrated in FIG. 5.
However, with complementary RA signal RAB00 low between times t202 and t203, transistor T4 is turned off which disables current path 1 as illustrated in FIG. 5. With RA signal RA00 high between times t202 and t203, transistor T3 is turned on. Because main word line MWL00 is low during this time, any charge removed from sub-word line SWL0000 goes through current path 3 as illustrated in FIG. 5.
At time t203, complementary RA signal RAB00 returns high and RA signal RA00 returns low. Thus, after time t203, any charge removed from sub-word line SWL0000 goes through current path 1 as illustrated in FIG. 5.
Referring now to FIG. 9, a circuit schematic diagram illustrating portions of circuits used to activate sub-word lines SWL is set forth.
It can be seen that a buffer BF0 is used to drive main word line MWL00. Buffer BF0 is made up of two inverters including complementary IGFETs (n-type and p-type). Buffer BF0 includes a transistor TB0 to pull main word line MWL00 low. Transistor TB0 is an n-type IGFET. Thus, in the time between time t202 and t203 illustrated in FIG. 8, the charge removed from sub-word line SWL0000 going through current path 3 as illustrated in FIG. 5, also goes through transistor TB0 in buffer BF0.
It is noted in FIG. 9 that in the conventional approach, buffers (BF0, BF1, . . . ), RA drivers RAD, and sub-decoder blocks SB receive the word line ground potential GNDXDEC to provide a low potential to unselected sub-word lines SWL.
Referring now to FIG. 10, a circuit schematic diagram of an RA driver is set forth.
RA driver in FIG. 10, illustrates RA driver RAD1A which generates RA signal RA00 and complementary RA signal RAB00. Also illustrated is RA driver RAD1B, which generates RA signal RA02 and complementary RA signal RAB02. Reference characters for RA driver RAD1B are illustrated in parenthesis. Collectively, RA drivers (RAD1A and RAD1B) make up RA driver RAD1 illustrated in FIGS. 1 and 2.
RA driver RAD1A includes decoder 100, AND gate 101, inverters (102 and 103), and transistors (104 and 105). Decoder 100 receives row addresses (X0 and X1) as inputs and generates an output received at an input of AND gate 101. AND gate 101 receives control signal RAE at another input and provides an output to the inputs of inverters (102 and 103). Inverter 103 provides complementary RA signal RAB00 as an output. Inverter 102 provides an output to the gates of transistors (104 and 105). Transistor 104 has a source connected to a boosted power supply potential and a drain connected to RA signal RA00. Transistor 105 has a source connected to a word line ground potential GNDXDEC and a drain connected to RA signal RA00. Transistor 104 is a p-type IGFET. Transistor 105 is an n-type IGFET.
A peripheral ground potential GND is connected as a ground for decoder 100, AND gate 101, and inverters (102 and 103).
When control signal RAE is low, the output of AND gate 101 is low. With the output of AND gate 101 low, RA signal RA00 is low and complementary RA signal RAB00 is high.
When control signal RAE is high, and row addresses (X1, X0) are in a select state, which for decoder 100 of RA driver RAD1A is {low, low}, then the output of decoder 100 becomes high. With the output of decoder 100 high and control signal RAE high, the output of AND gate 101 becomes high. With the output of AND gate 101 high, RA signal RA00 is high and complementary RA signal RAB00 is low. If decoder 100 of RA driver RAD1A receives row addresses (X1, X0) having a value other than {low, low}, then the output of decoder 100 is low, RA signal RA00 is low, and complementary RA signal RAB00 is high.
In order to sink sufficient current to discharge RA signal RA00, transistor 105 needs to be relatively large as compared to other transistors.
RA driver RAD1B operates in the same general manner as RA driver RAD1A except decoder 100xe2x80x2 is enabled and outputs a logic high when row addresses (X1, X0) have the value of {low, high}, respectively.
Other decoders (RAD2, RAD3, RAD4, and RAD5) have similar circuit construction to RA driver RAD1.
Peripheral ground GND and word line ground GNDXDEC are connected to the same ground pad through separate wirings. Variations of the potential on the separate grounds are isolated with the aid of wiring resistance R1 and wiring resistance R2 of the respective wirings. This can prevent noise on the respective wirings from being transmitted between the separate grounds.
Current paths and ground noise during sub-word line switching will now be illustrated with reference to FIG. 11 in conjunction with FIG. 9.
Referring now to FIG. 11, a timing diagram illustrating current paths for transferring charge to and from a sub-word line is set forth.
The timing diagram of FIG. 11 illustrates current paths from sub-word lines SWL when selected and unselected.
The timing diagram of FIG. 11 includes row address XADD, main word line MWL00, control signal RAE, RA signal RA00, complementary RA signal RAB00, sub-word line SWL0000, sub-word line SWL0002, sub-word line SWL0100, and sub-word line SWL0102. Also illustrated is a blown up portion around time t304, illustrating a selected sub-word line SWL0000 and word line ground potential GNDXDEC.
The timing diagram of FIG. 11 illustrates selected signals in the circuit schematic diagram of FIG. 9.
In the timing diagram of FIG. 11, sub-word line SWL0000 changes from the unselected state (low) to the selected state (high) and back to the unselected state, while the other illustrated sub-word lines (SWL0002, SWL0100, and SWL0102) remain in the unselected state.
Initially main word lines (MWL00 and MWL01) are low. RA signals (RA00 and RA02) are also low. Complementary RA signals (RAB00 and RAB02) are high. As illustrated in FIG. 11, before time T300, each sub-word line (SWL0000, SWL0002, SWL0100, and SWL0102) is held at a low level by way of respective current paths 1 (FIG. 5) within their respective sub-decoder block SB.
At time t300, row address XADD changes to a value to select sub-word line SWL0000. Referring to FIG. 9, a high potential at a boosted voltage level is input from row decoder XDEC1 to the input of buffer BF0. After a propagation delay, at time t301, main word line MWL00 transitions to a high level. The high level is a boosted voltage level.
At time t301, because main world line MWL00 becomes high, the potential at node A of sub-decoder blocks (SB0000 and SB0002) becomes high. With RA signals (RA00 and RA02) low, current paths 2 within sub-decoder blocks (SB0000 and SB0002) are enabled to hold sub-word lines (SWL0000 and SWL0002), respectively, low. Thus, both current paths (1 and 2) are enabled in sub-decoder blocks (SB0000 and SB0002) at time t301. However, for sub-decoder blocks (SB0100 and SB0102), only current path 1 is enabled.
At time t302, a control circuit (not shown) places control signal RAE in an enable state (transitions from low to high). Time t302 can be determined by a predetermined delay from the row address XADD change. RA driver RAD1 brings RA signal RA00 to a high level and complementary RA signal RAB00 to a low level.
As a result, at time t303, sub-word line SWL0000 is activated by sub-decoder block SB0000. When activated, sub-word line SWL0000 rises to a boosted potential. Sub-word line SWL0000 turns on the memory cell transistor of memory cell M1 and data stored on the memory cell capacitor is transferred to bit line BT2.
Because RA signal RA02 remains low, current paths (1 and 2) remain enabled within sub-decoder block SB0002.
However, when RA signal RA00 becomes high, transistor T3 within sub-decoder block SB0100 is turned on and current path 3 becomes enabled. Thus, sub-word line SWL0100 is held low by current path 3 through transistor T3 within sub-decoder block SB0100 and transistor TB0 within buffer BF1.
At time t304, a control circuit (not shown) places control signal RAE in a disable state (transitions from high to low). The time between times t302 and t304 can be determined by a predetermined delay indicating the maximum time required to access data in a memory cell. RA driver RAD1 brings RA signal RA00 to a low level and complementary RA signal RAB00 to a high level.
Thus, charge is drawn from sub-word line SWL0000 to bring the potential of sub-word line SWL0000 from a high boosted potential to ground or low. Because main word line MWL00 is high at time t304 and RA signal RA00 becomes low, current path 2 within sub-decoder block SB0000 is enabled. Also, because complementary RA signal RA00 becomes high at time t304, current path 1 within sub-decoder block SB0000 is enabled. Thus, sub-word line SWL0000 is discharged through current paths (1 and 2) within sub-decoder block SB0000 at time t304.
At time t304, the status of sub-decoder blocks (SB0002 and SB0102) remains unchanged. Current paths (1 and 2) within sub-decoder block SB0002 and current path 1 within sub-decoder block SB0102 remain enabled. However, when RA signal RA00 transitions low, current path 3 within sub-decoder block SB0100 becomes disabled. When complementary RA signal RAB00 transitions high, current path 1 within sub-decoder block SB0100 becomes enabled. Thus, sub-word line SWL0100 is held low by current path 1 within sub-decoder block SB0100 at time t304.
In order to improve cycle times of accessing a memory cell, the transistors in the discharge path of a sub-word line SWL are made relatively large. A sub-word line is connected to control gates of a very large number of memory cell transistors, thus it has a large capacitance. When sub-word line SWL0000 goes from the selected state to the unselected state at time t304, a large amount of current flows through current paths (1 and 2) to word line ground potential GNDXDEC. Also, RA signal (RA00 and RA02) are routed the length of a cell array CELL and are connected to diffusion regions (source/drain connections) of transistor T2 and gates of transistor T3 within a large number of sub-word decoders SB. Thus, the capacitance of RA signals (RA00 and RA02) is very large. This further increases the instantaneous current flowing to word line ground potential GNDXDEC.
Referring to FIG. 11, there is a blown up section illustrating sub-word line SWL0000, RA signal RA00, word line ground potential GNDXDEC, and non-selected sub-word lines (SWL0001, SWL0002, and SWL0003). When a large current flows to word line ground potential GNDXDEC, a noise bump can be induced due to the resistance of the signal carrying conductor. In this case, because word line ground potential GNDXDEC is holding non-selected sub-word lines low (through current path 1 or current paths 1 and 2), the noise bump can be transmitted on non-selected sub-word lines (for example, SWL0001, SWL0002, and SWL0003). This can cause unwanted leakage from memory cells connected to these non-selected sub-word lines and can compromise stored data. Although only sub-word lines (SWL0001, SWL0002, and SWL0003) are illustrated, other sub-word lines may have unwanted noise because they may be held to a low level by current flowing to word line ground potential GNDXDEC.
The purpose of providing a separate word line ground potential GNDXDEC from a peripheral ground potential is to eliminate unwanted noise on unselected word lines. In this case, this purpose may not be achieved.
One method of solving this problem is to increase the width of the wiring carrying word line ground potential GNDXDEC. This can reduce resistance and increase current carrying capability. However, this must be done for each memory block on the chip and can result in an increase in chip size, thus increasing production costs.
Another approach for solving this problem is to use a material with a reduced sheet resistance for the wiring carrying word line ground potential GNDXDEC. However, this can require a change in the fabrication process, which requires process developmental costs and costs for testing the design. This increases overall fabrication costs, thus increasing per chip costs of manufacturing.
In view of the above discussion, it would be desirable to provide a semiconductor memory device that may be capable of discharging a sub-word line at a high speed. It would also be desirable to reduce adverse effects such as memory cell leakage caused by discharging a sub-word line. It would be desirable to provide this while not increasing chip size as compared to conventional approaches.
According to the present embodiments, a semiconductor memory device having a peripheral ground line receiving charge when discharging a sub-word line is provided. The semiconductor memory device can include a row decoder, RA driver, and sub-decoder blocks. The row decoder may activate a main word line based on a received address value. RA driver may activate a sub-decoder block from a group of sub-decoder blocks coupled to the activated main word line. RA driver may provide a current path to the peripheral ground when the sub-word line transitions from the activated state to the unactivated state. Non-selected sub-word lines may have a current path to a word line ground for holding the other word lines at a xe2x80x9cquietxe2x80x9d ground potential. Noise produced from discharging a sub-word line may have a reduced affect on non-selected sub-word lines.
According to one aspect of the embodiments, a semiconductor memory device may include a plurality of word lines. Each word line may be connected to a plurality of memory cells. A decoder circuit may be coupled to a predetermined word line. The decoder circuit may provide an electrical connection between a first ground line and the predetermined word line when the predetermined word line is not selected. The decoder circuit may provide an electrical connection between a second ground line and the predetermined word line when the predetermine word line is deactivated.
According to another aspect of the embodiments, the decoder circuit may include a first transistor providing an electrical connection between the predetermined word line and the first ground line and a second transistor providing the electrical connection between the predetermined word line and the second ground line.
According to another aspect of the embodiments, the current capacity of the second transistor may be larger than the current capacity of the first transistor.
According to another aspect of the embodiments, the second transistor may be an insulated gate field effect transistor (IGFET).
According to another aspect of the embodiments, when the predetermined word line is deactivated, the second transistor may be controlled with a boosted potential.
According to another aspect of the embodiments, the plurality of word lines may include a plurality of main word lines. Each main word line may be divided into a plurality of sub-word lines. The decoder circuit may provide the electrical connections between the first and second ground lines and a predetermined sub-word line.
According to another aspect of the embodiments, a value of an internal row address may activate the predetermined word line. The predetermined word line may be deactivated prior to a subsequent change in the value of the internal row address.
According to another aspect of the embodiments, a semiconductor memory device may include a first word line having an activated state and an unactivated state. A second word line may have an activated state and an unactivated state. A decoder circuit may provide a discharge current path to a first ground line when the first word line transitions from the activated state to the unactivated state. The decoder circuit may provide a holding current path to a second ground line when the second word line is in the activated state.
According to another aspect of the embodiments, the decoder circuit may receive a control signal having a discharge current path enable state and a discharge current path disable state. When the first word line is in the activated state, the control signal may be in the discharge current path disable state.
According to another aspect of the embodiments, the holding current path may be disabled when the control signal is in the discharge current path enable state.
According to another aspect of the embodiments, a first control signal may have an enable state and a disable state. The decoder circuit may include an address decode portion. The address decode portion may provide a decode signal having a decode select state when a received address has a predetermined value and a decode unselected state when the received address does not have the predetermined value. The holding current path may be disabled when the first control signal has the enable state and the decode signal has the first decode state.
According to another aspect of the embodiments, the discharge current path may be disabled when the decode signal has the decode unselected state.
According to another aspect of the embodiments, a second control signal may have a second control enable state and a second control disable state. The discharge current path may be enabled when the second control signal has the second control signal enable state and the decode signal has the decode enable state.
According to another aspect of the embodiments, a method for accessing a memory cell of a semiconductor memory device may include the steps of: activating a first word line electrically connected with a gate of an access transistor of a memory cell, keeping a second word line unactivated by providing a first holding current path to a first ground line, and deactivating the first word line by providing a first discharge current path to a second ground line.
According to another aspect of the embodiments, the first holding current path may have a smaller current capacity than the first discharge current path.
According to another aspect of the embodiments, the first word line may have a second holding current path when unactivated. When the first discharge current path is enabled, the second holding current path may be disabled.
According to another aspect of the embodiments, the first discharge current path may include an insulated gate field effect transistor (IGFET). The IGFET may have an impedance path coupled between the first word line and the second ground line.
According to another aspect of the embodiments, deactivating the first word line may include applying a boosted voltage to the gate of the IGFET.
According to another aspect of the embodiments, the step of activating a first word line may include activating a first main word line coupled to a first group of word lines and activating the first word line from the first group of word lines.
According to another aspect of the embodiments, the step of activating the first word line may include internally receiving a row address. The step of deactivating the first word line is prior to internally receiving a subsequent row address.